Synthesis of High-Performance Packet Processing Pipelines

Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We propose a high-level synthesis technique for a new model for representing packet editing functions. Experiments show our circuits achieve a throughput of up to 40Gb/s on a commercially available FPGA device, equal to state-of-the-art implementations

Synthesis and Optimization of Pipelined Packet Processors

We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput. Our functional model provides a level of abstraction familiar to a network protocol designer; in particular, it does not require knowledge of register-transfer-level hardware design. Our synthesis tool implements the specified function in a sequential circuit that processes packet data a word at a time. Finally, our analysis technique computes the maximum throughput possible from the modules and then determines the smallest buffers that can achieve it. Experimental results conducted on industrial-strength examples suggest that our techniques are practical. Our synthesis algorithm can generate circuits that achieve 40 Gb/s on field-programmable gate arrays, equal to state-of-the-art manual implementations, and our buffer-sizing algorithm has a practically short runtime. Together, our techniques make it easier to quickly develop and deploy high-speed network switches

Applying reconfigurable computing to reconfigurable networks

Considerable research has been recently directed towards building flexible and reconfigurable network infrastructures, which promise to provide better functionality and allow faster evolution in services. Two classes of reconfigurable networks have been investigated: adaptive protocols and programmable (active) networks. An adaptive protocol can modify itself and dynamically optimize its structure in the face of changing network conditions. A second technology, programmable (or active) networks have been proposed as a way of accelerating the deployment and support of new network services. Several software-only prototypes of each technology (adaptive protocols and active networks) have been built. Performance limitations and a tacit assumption that protocol flexibility requires software has generated a considerable amount of skepticism towards these approaches. We make three major contributions in this thesis. First, we demonstrate how results in the field of Reconfigurable Computing can be applied in constructing a reconfigurable network protocol, improving the performance by delegating “bit-intensive” functions to hardware. Second, we extract the safety and security issues discovered in prototyping and generalize them to any architecture using programmable logic. Third, this thesis completes the research in Protocol Boosters, a project in the field of adaptive protocols, which was considered incomplete prior to this work. The methodology we use is evaluation of a proof-of-concept through design and implementation. Our experimental platform, the Programmable Protocol Processing Pipeline (P4) is optimized for network processing and composes a set of field-programmable logic arrays (FPGA) into a processing engine achieving the processing performance of special purpose hardware with the software-like flexibility. Using the P4 and one of the proposed frameworks for building adaptive and programmable protocols, we demonstrate that reconfigurable hardware can be used for building reconfigurable networks. This demonstrates that on-the-fly hardware programmability can be applied in many settings such as line cards, switches and routers

Applying reconfigurable computing to reconfigurable networks

Considerable research has been recently directed towards building flexible and reconfigurable network infrastructures, which promise to provide better functionality and allow faster evolution in services. Two classes of reconfigurable networks have been investigated: adaptive protocols and programmable (active) networks. An adaptive protocol can modify itself and dynamically optimize its structure in the face of changing network conditions. A second technology, programmable (or active) networks have been proposed as a way of accelerating the deployment and support of new network services. Several software-only prototypes of each technology (adaptive protocols and active networks) have been built. Performance limitations and a tacit assumption that protocol flexibility requires software has generated a considerable amount of skepticism towards these approaches. We make three major contributions in this thesis. First, we demonstrate how results in the field of Reconfigurable Computing can be applied in constructing a reconfigurable network protocol, improving the performance by delegating “bit-intensive” functions to hardware. Second, we extract the safety and security issues discovered in prototyping and generalize them to any architecture using programmable logic. Third, this thesis completes the research in Protocol Boosters, a project in the field of adaptive protocols, which was considered incomplete prior to this work. The methodology we use is evaluation of a proof-of-concept through design and implementation. Our experimental platform, the Programmable Protocol Processing Pipeline (P4) is optimized for network processing and composes a set of field-programmable logic arrays (FPGA) into a processing engine achieving the processing performance of special purpose hardware with the software-like flexibility. Using the P4 and one of the proposed frameworks for building adaptive and programmable protocols, we demonstrate that reconfigurable hardware can be used for building reconfigurable networks. This demonstrates that on-the-fly hardware programmability can be applied in many settings such as line cards, switches and routers

On-the-fly Programmable Hardware for Networks

Ongoing research in adaptive protocols and active networks has presumed that flexibility is offered exclusively through software systems, and the performance implications have generated considerable skepticism. The Programmable Protocol Processing Pipeline (P4) exploits the dynamic reconfigurability of RAM based Field Programmable Gate Arrays (FPGAs) to provide both hardware performance and dynamic functionality to network components. We use forward error correction (FEC) as an example of a protocol processing function. Our measurements show that the P4 is able to process the data stream at OC-3 (155 Mbps) link rate, and consequently improve TCP performance in noisy environments. 1 Introduction A desire for flexible network infrastructures has stimulated research into adaptive protocols and active networks. This research[14] has presumed that flexibility is offered exclusively through software systems, and the performance implications have generated considerable skepticism. In particu..

P4: A Platform for FPGA Implementation of Protocol Boosters

. Protocol Boosters are functional elements, inserted and deleted from network protocol stacks on an as-needed basis. The Protocol Booster design methodology attempts to improve end-to-end networking performance by adapting protocols to network dynamics. We describe a new dynamically reconfigurable FPGA based architecture, called the Programmable Protocol Processing Pipeline (P4), which provides a platform for highly-flexible hardware implementations of Protocol Boosters. The prototype P4 is designed to interface to an OC3 (155 Mb/s) ATM link and perform selected boosting functions at this line rate. The FPGA devices process the data stream as a pipeline of processing elements. Processing elements are downloaded and activated dynamically, based on policies used by the controller to choose configurations. As modules become unnecessary they are removed from the pipeline chain. 1 Introduction Network protocols are designed to meet application requirements for data communications, includi..

FPGA Viruses

. Programmable logic is widely used, for applications ranging from field-upgradable subsystems to advanced uses such as reconfigurable computing platforms which are modifiable at run-time. Users can thus implement algorithms which are largely executed by a general-purpose CPU, but may be selectively accelerated with special purpose hardware. In this paper, we show that programmable logic devices unfortunately open another avenue for malicious users to implement the hardware analogue of a computer virus. We begin the paper with an outline of the general properties of FPGAs that create risks. We then explain how to exploit these risks, and demonstrate through directed experiments that they are exploitable even in the absence of detailed layout information. We prove our point by demonstrating the first known FPGA virus and its effect on the current absorbed by the device, namely that the device is destroyed. We close by outlining possible methods of defense and point out the similarities ..